Technical documentation is a guideline.

I have been using an Analog Devices ADC for a project. It's an AD7685, 16-bit with SPI. It works with a SPI bus, but not unless you have a SPI master that is more flexible than pretty much anything that I have ever seen. One cannot just attach the device and have the SPI bus communicate. The chip select line controls the conversion, and the MOSI line controls the 'mode behavior'. The /CS line needs to be double dipped, and because the device has an internal clock, it seems to be very picky about the timing.

I've modified Figure 35 for the datasheet. Have you ever seen a /CS line with this behavior? The other thing is that the image suggests that the /CS line can be unasserted after the initial rising edge that starts the conversion.

Here's the reality of functionality. The datasheet states that there needs to be minimum of 3.2uS between the rising edge on /CS and the data to be valid to be clocked out. I can tell you that they are absolutely correct, and the device is finicky about this timing. If you happen to get leading '1's in your data value, you have violated this setup time. If you reach 10uS between /CS and clocking, I also received incorrect sample data on the bus.

I was trying to be smart and get this double-dip /CS from the previous SPI request or in some other way, but because MOSI needs to be '1' when /CS goes low, you basically need to dedicate this bus time exclusively to this IC. Considering that this setup time takes as long as the total data transfer, it is very disappointing.

In summary, the failure mode of violating SPI (which this barely qualifies) timing is the MSB being '1's of your data sample and you will need to bit bang the SPI unless you are lucky enough to have control over the logic in your SPI controller.